This invention relates to an inductor.
It is well known to provide spiral inductors to realise devices such as voltage controlled oscillators (VCOs) in, for example, a transceiver in an integrated circuit (IC).
An inductor can be characterised, inter alia, in terms of its resonant frequency ω, which is a function of the self inductance L of the inductor, and the parasitic capacitance C of the inductor:
                    ω        =                  1                      LC                                              (        1        )            Another characteristic of an inductor is its Quality factor (Q-factor):
                    Q        =                              ω            ⁢                                                  ⁢            L                    R                                    (        2        )            where R is the internal resistance of the inductor, and ωL is the inductive resistance of the inductor.
From equation (1), it can be seen that the resonant frequency of an inductor can be increased by minimising the parasitic capacitance. There are two main contributors to the parasitic capacitance of an inductor in an IC: (i) capacitance between the conductive track (which makes up the inductor turns (windings) of the inductor) and the substrate (e.g. semiconductor substrate) on which the inductor is formed, and (ii) capacitance between the inductor turns themselves.
From equation (2), it can be seen that the Q-factor of an inductor is linked to the resonant frequency ω, such that an inductor having a higher resonant frequency also tends to have a higher Q-factor.
FIGS. 1A and 1B schematically illustrate the layout of the windings of a three turn (FIG. 1A) and a four turn (FIG. 1B) inductor. The inductors shown in FIGS. 1A and 1B do not form embodiments of this invention but are instead described herein to provide counter examples of conventional inductor layouts, for comparison with the embodiments described below in relation to FIGS. 3-8.
In FIG. 1A, the inductor 10 includes a conductive track which forms three inductor windings. The conductive track begins at terminal 12 and ends at terminal 14. The inductor 10 shown in FIG. 1A (and also the inductor shown in FIG. 1B) is provided with a centre tap 16 for use in, for example, differential VCO applications. The inductors shown in FIGS. 1A and 1B are substantially symmetrical, in order to allow correct placement of the centre tap 16. In this example, the inductors shown in FIGS. 1A and 1B are also substantially octagonal.
As is shown in FIG. 1A, the inductor includes two crossing points. These crossing points are distributed around the inductor windings such that a first crossing point 24 is provided in the vicinity of the terminals 12 and 14, while the crossing point 22 is provided on an opposite side of the inductor windings, substantially in line with the centre tap 16.
The four turn inductor shown in FIG. 1B has a similar configuration to the three turn inductor shown in FIG. 1A, and includes a first crossing point 24, and second and third crossing points 22 and 23.
The purpose of the crossing points provided in the inductors of FIG. 1A and FIG. 1B is to allow the inductor windings to be formed while enabling the terminals 12 and 14 to connect on the outside of the inductor. Thus, in both FIG. 1A and FIG. 1B, the terminal 12 and the terminal 14 feeds to or feeds from the outermost part of the conductive track, whereby effective connection to the conductive track at the terminals can be made.
The layouts shown in FIGS. 1A and 1B each have associated therewith a given amount of parasitic capacitance that results from capacitance between the various windings of the inductor. FIG. 2 shows a model by which the total parasitic capacitance for an inductor resulting from parasitic capacitance between the inductor turns can be calculated.
An inductor having a voltage V applied across its terminals, and having a number of turns n, has a total parasitic capacitance which can be approximated by:
                              C          eff                =                              ∑            i                    ⁢                                    1              2                        ⁢                          V              i              2                        ⁢                          C              i                                                          (        3        )            where Vi is the average voltage between the ith pair of adjacent inductor turns, and Ci is the intrinsic capacitance between the ith pair of adjacent inductor turns. Thus, to a first order of approximation (ignoring contributions from non-adjacent portions of the conductive track), an inductor having i adjacent inductor turns has a total parasitic capacitance which is the sum of the parasitic capacitance between all of the adjacent pairs of inductor turns in the inductor.
Turning again to FIGS. 1A and 1B, and assuming that there is a substantially linear voltage drop along the conductive track between the terminal 12 and the terminal 14 of the inductor 10, it can now be seen that according to equation 3, the arrangement of the turns in the inductor 10 has a direct effect upon the overall parasitic capacitance of the inductor. This is because, according to equation 3, the contribution to the total parasitic capacitance arising from a given pair of adjacent inductor turns depends upon the voltage difference between those two adjacent inductor turns, and because the voltage difference between adjacent inductor turns depends directly upon the way in which the inductor turns are laid out.
Therefore, according to the invention, it has for the first time been realised that by designing an inductor layout (e.g. a substantially symmetrical inductor layout) in which the adjacent inductor turns on the whole have a relatively low potential difference there between, the overall parasitic capacitance of the inductor can be reduced, and the resonant frequency and Q-factor of the inductor can thereby be increased.